1. Field of the Invention
The present invention relates to a semiconductor memory device for transferring to be stored to or read from a memory cell array through input/output lines, and more particularly to a semiconductor memory device which selects the input/output lines by using column addresses.
2. Description of the Related Art
On a semiconductor memory device, such as a dynamic RAM, a predetermined memory cell is selected by selecting one of a plurality of word lines and one of a plurality of column select lines. The word line is selected by a row address signal latched in response to activation of a row address strobe signal RAS and a bit line is selected by a column address signal latched in response to activation of a column address strobe signal CAS.
When reading data from or writing data to the selected memory cell, a selected one of a plurality of column selection switches connects an input/output line pair to a corresponding sense amplifier at an appropriate time. Furthermore, upon transfer of the data bit through the sense amp to a corresponding pair of input/output lines, the input/output lines develop complementary potentials through charge sharing. At this moment, unselected input/output line pairs are equalized and precharged to a predetermined potential.
FIG. 1 shows the connection between a sub memory cell array and input/output line pairs in a conventional dynamic RAM and FIG. 2 shows timing therefore. The sub memory cell array is comprised of k word lines WL0 through WLK-1, m bit line pairs BL0 through BLm-1 and BLO-BLM-1, and (k.times.m) memory cells 10. A plurality of column selection switches 20 are each connected between m sense amplifiers SA connected to the bit line pairs and the input/output lines pairs.
A typical dynamic RAM is divided into four memory banks each including a number of sub memory cell arrays having a folded bit line structure. The dynamic RAM may have more than four memory banks. For instance, a 16 Mbit DRAM includes memory banks of 4 Mbits each, which are each divided into 16 sub memory cell arrays. The sub memory cell array of FIG. 1 has 256 Kbits including 256 word lines (k=256) and 1024 (1K) bit lines (m=1024).
The input/output line pairs I/O0, I/O0, I/O1 and I/O1 are arranged to one side (i.e. the left hand side of FIG. 2) of the sub memory cell array. The input/output line pairs I/O0', I/O0', I/O1' and I/O1' are arranged to an opposite side (i.e. the right hand side of FIG. 2) of the sub memory cell array. The input/output line pairs constitute an input/output bus which is shared by the adjacent sub memory cell arrays. That is, the input/output line pairs I/O0, I/O0, I/O1 and I/O1 arranged on the left hand side of the sub memory cell array constitute a left input/output bus and the input/output line pairs I/O0', I/O0', I/O1', and I/O1' arranged on the right hand side of the sub memory cell array constitute a right input/output bus. The input/output lines in the respective data busses transfer 2-bit data, alternatively. Column selection lines CSL0 through CSLi-1 are respectively connected to and control the column selection switches 20 corresponding to the respective bit line pairs having the 2-bit data. Therefore, if any one column selection line is activated, 2-bit data are transferred respectively through the left and right input/output buses. A total of four bits of data are transferred in the dynamic RAM device for each active column select line CSL0 through CSLi-1.
As shown in FIG. 2, the input/output line pairs I/O0, I/O0, I/O1,2, I/O0', I/O0' I/O1' and I/O1' are equalized and precharged to a precharged level, which is commonly a value determined by subtracting a threshold voltage of an NMOS transistor from a power supply voltage, in response to an input/output line precharge signal. The input/output line pairs are developed to a "high" state and to a "low" state when any one of the column selection lines is activated to a "high" state. Alternatively, the input/output line pairs are all equalized and precharged to the precharge level in response to the input/output line precharge signal when none of the column selection lines are activated.
As an example of the operation, if the column selection signal CSL0 is activated to a "high" state, the 2-bit data read from the bit line pairs BL0, BLO, BL1 and BL1 are transferred to the left input/output bus, i.e., two input/output line pairs I/O0, I/O0, I/O1 and I/O1, via the respective sense amplifiers and the column selection switches 20, and developed according to the potential of the data bits. At the same time, the 2-bit data read from the bit line pairs BL2, BL2, BL3 and BL3 are transferred to the right input/output bus, i.e., two input/output line pairs I/O0', I/O0', I/O1' and I/O1', via the respective sense amplifiers and the column selection switches 20 and developed according to the potential of the data bits. After the data developed on the input/output line pairs I/O0, I/O0, I/O1, I/O1I/O0', I/O0', I/O1' and I/O1' are transferred to a data bus and a data output buffer (not shown) in the dynamic RAM, the developed input/output lines pairs are equalized and precharged in response to the input/output line precharge signal to be ready for a subsequent transfer of the next data bits. Subsequently, if the column selection line CSL1 is activated to a "high" state, 2-bit data read from the bit line pairs are transferred to the input/output line pairs I/O0, I/O0, I/O1 and I/O1 and 2-bit data read from the bit line pairs BL6, BL6, BL7 and BL7 are transferred to the input/output line pairs I/O0', I/O0', I/O1' and I/O1', so that input/output line pairs I/O0, I/O0, I/O1, I/O1, I/O0', I/O0', I/O1' and I/O1' are developed in the same manner as mentioned above with respect to the activation of CSL0.
In the conventional semiconductor memory device, when column selection lines are activated, all of the left and right input/output buses (4 bits of data) are first developed to reflect the data and then precharged and equalized to be prepared for the next data transfer. The conventional memory device, therefore, has a disadvantage because the speed of the device is limited by the amount of time required to equalize and precharge the input/output line pairs between accesses of the memory cells. Whenever a column selection line is activated, the 2-bit data are developed on all four input/output line pairs constituting the left and right input/output buses. Further, between the times when the four bits of data are developed in the input/output line pairs, an amount of time is necessary for precharging and equalizing the input/output line pairs before the next pairs of 2-bit data are developed. Therefore, the conventional device is limited because extra time must be used to ensure that a sufficient amount of time is allocated between accesses of the input/output line pairs so that both the data transfer operation and the precharge operation are completed. Thus, this limits the data transfer rate in a conventional memory device.